Analog multiplying circuit



1961 A. E. GLANDON 2,996,252

ANALOG MULTIPLYING CIRCUIT Filed Aug. 22, 1958 2 Sheets-Sheet 1 Fig.

ADRIAN E. GLA/VDO/V INVENTOR.

ATTORNEYS Aug. 15, 1961 A. E. GLANDON 2,996,252

ANALOG MULTIPLYING CIRCUIT Filed Aug. 22, 1958 2 Sheets-Sheet 2 Fig. 3

6 I? 6' ADRIAN E. GLA/VDO/V 7 INVENTOR.

A TTORNEYS United States Patent The present invention concernsmultiplying circuits and more particularly concerns analog multiplyingcircuits wherein a multiplying factor is adjustable both in sign and innumerical value.

Frequently there is a need for an electronic circuit capable ofmultiplying an input signal by a factor that is adjustable in numericalvalue. By means of various known circuits it is possible to multiply aninput signal by a factor of fixed sign, the multiplying factor beingadjustable in numerical value over a limited range. For example, asimple potentiometer may be regarded as per-forming the operation ofmultiplying by a positive factor whose numerical value is adjustablebetween zero and unity. If an amplifier is connected to the output ofthe potentiometer, it extends the range of numerical values of themultiplying factor beyond unity. Initially, the multiplying factor maybe made postive or negative by using an even or odd number of amplifyingstages, respectively, but its sign cannot be made selectively reversibleby simple means.

It is therefore a principal object of the present invention to multiplyan input signal voltage by a factor that may be set at any selectednumerical value within a range bounded by positive and negative limits.

Another object is to select the numerical value of a multiplying factor,within a range bounded by positive and negative limits, by themanipulation of a single control device.

Other objects are:

To selectively adjust the relationship between input voltage level andZero output voltage in an analog multiplying circuit;

To independently and selectively adjust both the algebraic numericalvalue of a multiplying factor and the relationship between input voltagelevel and zero output voltage in an analog multiplying circuit; and

To provide an improved analog multiplying circuit.

Other objects of the invention will appear from the followingdescription, reference being made to the accompanying drawings, wherein:

FIG. 1 is a schematic wiring diagram of a simple form of the invention;

FIG. 2 is a graph illustrating the relationship between input and outputvoltages of'the circuit shown in FIG. 1;

FIG. 3 is a schematic wiring diagram of an alternate embodiment of theinvention; and

FIG. 4 is a graph illustrating therelationship between input and outputvoltages of the circuit shown in FIG. 3.

The present multiplying circuit incorporates one or two operationalamplifiers of the type commonly used in analog computers, and described,for example, in chapter 5, Electronic Analog Computers, by Kern andKorn, McGraw-Hill, 1952. The pertinent characteristics of each amplifierare: (1) gain may be expressed as a large negative number; (2') outputimpedance is relatively. low,

2,996,252 Patented Aug. 15, 1961 so that the amplifier may be used toprovide an input signal for similar amplifiers with negligible loadingof its output circuit; (3) the amplifier may be operated with arelatively large value of negative voltage feedback, sufficient to makevariations in amplifier gain negligible; and (4) the amplifier frequencyresponse extends to zero frequency, rendering the circuit useful foroperating upon D.C. signals as well as upon A.C. signals in the subaudioand audio frequency ranges.

The multiplying circuit of the present invention comprises an inputcircuit, an output circuit and two parallel channels interconnecting theinput and output circuits. The output circuit may include an operationalamplifier, designated the output amplifier, which sums the signalsreceived from the two channels. One channel applies the input signal tothe output amplifier without inverting the phase of the signal. Theother channel inverts the phase of the input signal, by means of anotheroperational amplifier, for example, before applying it to the outputamplifier. Thus, the output amplifier receives the input signal bothinverted and uninverted in phase.

In at least one channel, there is provided a device for attenuating amanually selectable portion of the input signal. Therefore, the totalsignal applied to the summing amplifier can be varied both in amplitudeand in phase, or algebraic sign, between limits which are determined bythe parameters of the channel components.

7 The overall output of the multiplying circuit can be expressed as theproduct of the input signal and a factor which is adjustable betweenpositive and negative limits.

Referring to FIG. 1, the multiplying circuit includes; an input terminaldesignated c to represent an input signal. Terminal e is connected inseries with a first. channel comprising only a resistor R A secondchannel,

connected in parallel with the first channel, comprises a.

resistor R in series with a phase inverter (comprising an operationalamplifier A a potentiometer R and a re-- sistor R A resistor R is inparallel with amplifier A and its resistance value may be chosenrelative to that of resistor R to produce any desired gain in amplifierA in a manner well known in the art, the gain being The two channels arejoined to the input of a second? amplifier A which is connected, inparallel with a resistor R to an output terminal designated 6 torepresent an output signal.

The operation of the circuit is as follows. A voltagesignal'appliedztothe input terminal e is transmitted to the output amplifier A througheach of the two channels:- (1) through resistor. R involving no phaseinversion;- and (2) through the channel including amplifier A resistors'R R R and potentiometer R The signalv through the latter channel isinverted in phase by'ampli fier A amplified by an amount determined bythe values of resistors R and R attenuated by an amount determined bythe setting of the potentiometer R (where a is the fraction of theoutput signal of amplifier A trans-- mitted by the potentiometer), andapplied through re-- sistor R to-the, input of amplifier A AmplifierAperforms a summing operation on the two signals applied to it throughresistors R and R and amplifies the two signals in amounts determined bythe values of resistors R R and R Thus, amplifier A receives two signalsopposed in phase or polarity. The relative magnitudes of these signalsdepend upon the relative degrees of amplification or attenuationoccurring in the two signal channels. Amplifier A therefore produces anoutput signal e related in amplitude and phase to the input signal s ina manner depending upon the setting of the potentiometer R and upon thevalues of resistors R R R R and R Expressed mathematically,

The operation of the circuit may be most clearly demonstrated byconsidering the special case in which equal positive and negativemaximum values of the multiplying factor are desired. For that case, wechoose R =R and Then Equation 1 becomes, upon substitution of therelationships in Equations 2 and 3,

where la0.

Substituting in Equation 4 some particular values for a,

FIG. 2 is a graph showing the input-output voltage relationship forvarious settings of potentiometer R The slope of each curve constitutesa numerical index of this relationship.

It will be understood that the above analysis is based upon the circuitas illustrated in FIG. 1. A similar analysis applies to the use of anadjustable attenuating device, such as potentiometer R in the firstchannel rather than in the second, i.e., in the channel opposite to thatwherein amplifier A is located. Furthermore, the attenuator can beplaced in the input to amplifier A rather than in its output circuit.that even greater flexibility in the multiplying factor can be achievedby using an adjustable attenuator in each channel, although two manualadjustments are then necessary to realize the full range of multipliervalues.

and differentiating Equation 8 with respect to the variable en:

ti a a e a -an I m t.

Setting Equation 10 equal to zero to specify the condition in whichoutput voltage is independent of the value of a, and solving for thecorresponding relationship between 6 and e Substituting Equation 11 inEquation 8 and equating e to zero to obtain the specified condition atzero output voltage,

When the values of resistors R R R and R satisfy Equation 12, the inputvoltage which produces zero output voltage is not affected by thesetting of the potentiometer R That is, when a is set at the value ofvoltage, as determined from Equation 11, which produces zero output, theoutput will remain at zero for any setting of 1:: potentiometer R Theeffect on the input-output voltage relationship of FIG. 2, caused by anadded input signal e is shown in FIG. 4 for a circuit meeting therequirements of Equations 2 and 12. It will be seen that the entire setof curves is displaced along the axis a by a distance repre- It alsowill be understood 2 I The input voltage required to obtain zero outputvoltby the voltage 2 as may be shown by'writing the equation for thiscircuit.

senting or the value of input voltage necessary to produce zero outputvoltage.

The invention has been described in detail with particular reference topreferred embodiments thereof, but it will be understood that variationsand modifications can be eifected Within the spirit and scope of theinvention as described hereinabove and as defined in the appended claim.

I claim:

An analog multiplying circuit comprising: a circuit input terminal; anamplifier having input and output terminals; a first channel comprisinga first resistor interconnectingsaid circuit input terminal and theinput terminal of said amplifier; a second channel interconnecting saidcircuit input terminal and the input terminal of said amplifier, saidsecond channel comprising in series connection a second resistor, aphase inverter and an adjusta'ble attenuator; and means to render theinput voltage 5 6 to said circuit required for zero output voltagetherefrom, References Cited in the file of this patent independent ofthe adjustment of said attenuator, said UNITED STATES PATENTS meansincluding a source of reference voltage; a third resistor connectingsaid source of said inverter; and a 2401779 Swartzel June 1946 fourthresistor connecting said source to said amplifier, 5 where R R R and Rrepresent said first, second, third REFEIFENCFTS and fourth resistors,respectively, and where 23 22 Engmeermg (Czalkowskl), August 1956,

Free. of the I.R.E. (Ragazzini et 'al.), May 1947, pp. R2 R3 1 444 452.

